1. Field of the Invention
This invention relates to methods and circuits for testing electronic devices.
2. Description of the Related Art
To ensure the quality and functionality of electronic devices, such as transistors in an integrated circuit, the devices are tested at various stages of fabrication. The test is usually performed using an automatic test equipment (xe2x80x9cATExe2x80x9d). The ATE injects test signals on the input pins of the device under test (xe2x80x9cDUTxe2x80x9d) and monitors the corresponding output. The output of the DUT is then compared to a known or expected value to determine if the DUT functions in accordance with its specifications.
As device geometry (feature size) becomes smaller, the output signals of devices correspondingly become faster and, unfortunately, also become more xe2x80x9cjittery.xe2x80x9d The jitter is introduced by noise coupling effects within the devices and is exacerbated by lower transistor threshold voltages and large current transients during switching. Further, when using low thermal mass integrated circuit packages, instantaneous semiconductor die temperature changes can occur and vary the timing of the output signals.
To alleviate jitter problems, device manufacturers have resorted to architectures wherein an output clock signal is provided along with an output data signal. Thus, data transfer is synchronized by a clock signal from the source device and not by a clock signal common to all devices in the system. Such output signals are referred to as source synchronous signals. Source synchronous signals are used in a variety of devices including Direct RAMBUS (xe2x80x9cRACxe2x80x9d) interfaces and high performance microprocessors. FIG. 1 shows waveforms for source synchronous signals 100 consisting of an output clock signal 101 and a corresponding output data signal 102 as xe2x80x9cseenxe2x80x9d by a receiving device during normal operation. Because the receiving device reads output data signal 102 relative to clock signal 101, very little data jitter is seen by the receiving device.
Although source synchronous signals are relatively stable during normal operation, jitter problems occur during device testing. FIG. 2 shows in a high level block diagram relevant portions of a typical ATE system in the prior art. ATE 200 is configured to test DUT 204, a source synchronous device. ATE 200 includes stimulus generators 201, a read/compare logic 202, a master clock 203, and other conventional portions not shown. Stimulus generators 201 inject test signals into DUT 204. The resultant output signals from DUT 204 are read and compared to an expected value by read/compare logic 202. Because the strobing of test signals into DUT 204 and the reading of the resultant output signals are performed relative to master clock 203 and not relative to the output clock signal of DUT 204, both the output data signal and output clock signal from DUT 204 appear jittery to ATE 200. FIG. 3 shows output data signal 102 and output clock signal 101 from DUT 204 as seen by ATE 200 relative to signals from master clock 203. The jitter in data signal 102 and clock signal 101 can cause false readings which render the test results unreliable or require very tight passing requirements (also known as xe2x80x9cguardbandsxe2x80x9d) on the ATE, with a consequential yield loss. Further, the jitter makes it difficult to test timing relationships, such as setup and hold times, between data signal 102 and clock signal 101. Thus, a method and apparatus for reliable testing of source synchronous devices are highly desirable.
The invention is directed to a method and associated apparatus for testing source synchronous devices using an ATE. An output data signal and an output clock signal of a source synchronous device are delayed using a programmable delay network. The delay provides the time required to deskew path errors and to buffer and distribute the output clock signal. The output data signal appears relatively stable to the ATE by reading the output data signal using the output clock signal.